A Field Guide
The AI Infrastructure
Atlas
Transistor to gigawatt, in nine plates.
Contents
- Foreword04
- The scope of the trade05
- How to read this Atlas06
- The nine plates
- Plate 0 · The transistor08
- Plate I · The die11
- Plate II · The HBM stack14
- Plate III · The module17
- Plate IV · The baseboard20
- Plate V · The chassis23
- Plate VI · The rack26
- Plate VII · The data hall29
- Plate VIII · The campus32
- Appendices
- Ticker index — 18 names, mapped to plates36
- Glossary of terms38
- Colophon & further reading40
Foreword
The AI trade is not a chatbot trade. Every dollar that reaches the companies drawn here passes through a piece of physical infrastructure — a five‑nanometer transistor etched onto a silicon wafer, a stack of high‑bandwidth memory plumbed through with copper pillars, a 72‑GPU (graphics‑processing unit) rack shedding heat into a stainless‑steel manifold, a substation stepping high‑voltage grid power down to something the servers can use. That infrastructure is expensive, it is slow to build, and it is made by a knowable list of public companies.
This Atlas is a field guide to that list. Nine plates, each a different scale of the same machine. At every tier we give you the plain‑language of what it is, why it matters to an equity investor, the bull and bear cases, the signals to watch, and the public tickers closest to the margin. Wherever a term of art appears for the first time, it is spelled out — HBM is high‑bandwidth memory, PPA is a power‑purchase agreement, and so on. A full glossary sits at the back.
The goal is simple: when the market panics over a chatbot, you should know exactly why the memory supplier, the liquid‑cooling integrator, and the merchant generator just got more valuable, not less. None of this is advice. It is a map. What you do with it is yours.
The scope of the trade
A sense of scale is the first thing most readers are missing. The companies in this Atlas are not a speculative bet on a new software category — they are the suppliers to the largest private capital‑expenditure cycle in the post‑war American economy.
$400 B+
Combined 2026 E capital expenditure from the four U.S. hyperscalers — Microsoft, Alphabet (Google), Meta, and Amazon — on data centers, chips, and power. For reference, the entire U.S. railroad industry spent ~$25 B in 2024.
~1.3%
Of U.S. gross domestic product (GDP, roughly $30 trillion in 2026), spent by just those four companies on AI infrastructure in a single year. Add Oracle, the neo‑clouds, Tesla, Stargate, and the utilities, and the number crosses 2%.
$500 B
Announced value of Project Stargate — OpenAI, Oracle, SoftBank, MGX — targeting ten gigawatts of dedicated AI campus capacity in the United States by 2029. A single multi‑year program nearly the size of the Apollo program in inflation‑adjusted dollars.
~$2 T
Cumulative private AI‑infrastructure spend expected across the 2024–2028 window, according to McKinsey and Morgan Stanley estimates. Roughly one generation of U.S. interstate highway construction, compressed into five years.
How this cycle compares
Measured as a share of GDP, the private AI buildout is on track to sit between the peak of the 1990s telecom overbuild (roughly 1% of GDP at its top) and the Apollo program at its 1966 peak (~2.2%). It is materially larger than the capital‑expenditure cycle that followed the 2001 oil price shock and comparable, in inflation- adjusted terms, to the interstate highway program of the 1950s and 60s. Unlike those earlier cycles, it is being funded largely by a handful of cash‑generative, investment‑grade technology companies rather than by the federal budget.
Where the dollars land
Roughly half of hyperscaler data‑center capex flows to silicon — GPUs (graphics‑processing units), custom ASICs (application‑specific integrated circuits), memory, and networking chips. The rest is split between the buildings (land, concrete, steel, mechanical/electrical/plumbing) and the power plant that feeds them (substations, transformers, generation contracts). The companies in this Atlas are mapped to exactly those three pillars: Silicon, Steel, and Power. If the capex number is right, and it has been raised every quarter for the past eight, the economics flow downstream to them automatically.
How to read this Atlas
Each plate is a scale
Plate 0 is the transistor — the smallest electrical switch in a GPU, only a handful of atoms wide. Plate VIII is a gigawatt campus — hundreds of acres, an on-site substation, eight halls the size of football fields. The plates in between each correspond to a step up in scale of roughly ten to a hundred. Every plate is the same machine, zoomed out by a factor.
Every plate repeats the same layout
One-line dek · schematic · specs table · plain-language description · why it matters to an investor · bull case / bear case · the signals that move the tier · the tickers closest to it.
Three pillars
WattsB4Bots covers the AI buildout through three pillars: Power (generation, transmission, cooling), Silicon (chips, memory, packaging, signal), and Steel (servers, racks, data halls, campuses). Each ticker in the index maps to a pillar and to one or more plates.
A note on numbers
All dollar figures are 2026 USD. Costs move; we refresh this document annually. Specifications favor the current NVIDIA-standard part (Hopper at the die level, Blackwell at the module level, GB200 NVL72 at the rack level).
Tier 0 · Silicon
The transistor
The atom of computing — a switch so small you need an electron microscope to see it.
0
The transistor
The atom of computing — a switch so small you need an electron microscope to see it.
Fig. 0 — The transistor. Schematic, not to scale.
- 1Gate — ~5 nm length
- 2Source
- 3Drain
- 4Fin — channel
Specs at a glance
- Feature size
- ~5 nm (0.000002 in)
- Density
- ~98 million / mm²
- Process node
- TSMC 4N (NVIDIA-custom)
- Switching rate
- ~2 GHz (2 billion / sec)
What it is
A FinFET (fin field-effect transistor) is the smallest unit of modern computing: a vertical silicon fin wrapped by a metal gate. Apply a voltage to the gate, the switch turns on and lets electrons flow from the source to the drain. Remove the voltage, the switch turns off. Every calculation a GPU (graphics-processing unit) does reduces, eventually, to billions of these switches flipping in coordinated patterns.
Why it matters to an investor
Transistor economics are the ground floor of the whole trade. When TSMC successfully ramps a new process node, every customer above them gets faster, cheaper, more power-efficient chips. When a node stalls — as happened with Intel's 10 nm — a generation of competitors gets a free ride. The $40 billion TSMC is spending per year on fabs is the capital expenditure that every other number in this atlas ultimately depends on.
Reading the tier
Bull case
TSMC's 2-nanometer (N2) process enters volume production in the second half of 2026. Even smaller A-class nodes (14 Å, 10 Å) follow. Every NVIDIA generation needs them — no one else can make leading-edge logic at volume.
Bear case
Geographic concentration. ~90% of the world's leading-edge silicon is fabricated on one island within flight range of a hostile military. A single cross-strait incident reprices the entire stack.
The signal to watch
TSMC monthly revenue release (usually the 10th of the month) and the quarterly earnings call are the cleanest read on what the whole AI buildout is actually consuming.
Reading the news
Headlines about ASML's High-NA EUV (extreme-ultraviolet) ramp, TSMC Arizona yields, and Samsung's GAA (gate-all-around) transistor recovery all move this layer. When Reuters reports “TSMC cuts N2 capex,” the whole stack above it re-prices.
Tickers closest to the margin
- TSMthe fab — makes every leading-edge chip
- ASMLthe only vendor on Earth for EUV (extreme-ultraviolet) lithography
- AMATdeposition & etch equipment
Tier I · Silicon
The die
Eighty billion switches laid out on a single square of silicon.
I
The die
Eighty billion switches laid out on a single square of silicon.
Fig. I — The die. Schematic, not to scale.
- 1SM grid — 132 active
- 2L2 cache — 60 MB
- 3HBM3 sites — 6 × on-package
Specs at a glance
- Size
- 27 × 30 mm (H100)
- Transistors
- 80 B (H100) · 208 B (B200)
- SMs / cores
- 132 SMs · 16,896 cores
- Silicon cost
- $3k–5k · sold $25k–40k
What it is
The die is what NVIDIA actually designs and TSMC (Taiwan Semiconductor Manufacturing Company) actually makes. A single piece of silicon the size of a postage stamp, carrying tens of billions of transistors organized into 132 Streaming Multiprocessors — compute clusters that run thousands of floating-point operations in parallel. The die is the unit of engineering achievement: everything above it in the atlas exists to keep one of these chips fed.
Why it matters to an investor
Die yield determines unit economics. A 30×30 mm die at TSMC 4N costs maybe $2,000 of silicon — but if yield drops 10%, the effective cost jumps 11%. NVIDIA's gross margin of ~75% is a function of the difference between silicon cost and a sold-module price of $30,000+. Every time TSMC improves yield, that margin gets reinforced.
Reading the tier
Bull case
Blackwell B200 fuses two dies into one package using TSMC's CoWoS-L (chip-on-wafer-on-substrate) advanced packaging — a capability that has become NVIDIA's moat at the system level. AMD MI350 and Intel Gaudi 3 trail by a generation.
Bear case
Packaging is the bottleneck now, not silicon. CoWoS (chip-on-wafer-on-substrate) capacity is sold out through 2026; TSMC is expanding but every delay means NVIDIA can't ship units it has already booked.
The signal to watch
NVIDIA's data-center revenue (reported quarterly) is the cleanest proxy for die shipments. When it grows 50% QoQ, packaging and memory suppliers are running flat out.
Reading the news
Quarterly: NVDA's data-center segment. Monthly: CoWoS capacity rumors out of Taipei. Any headline about "supply-constrained" on an NVDA call is a green light for memory and packaging names.
Tickers closest to the margin
- NVDAdesigns the chip
- TSMfabricates the silicon
- AMDInstinct MI300X — the only genuine GPU rival at scale
Tier II · Silicon
The HBM stack
The most expensive memory on Earth, stacked twelve layers high.
II
The HBM stack
The most expensive memory on Earth, stacked twelve layers high.
Fig. II — The HBM stack. Schematic, not to scale.
- 112 DRAM dies — 36 GB total
- 2TSVs — through-silicon vias
- 3Microbumps
- 4Buffer die
Specs at a glance
- Stack
- 12 DRAM dies + buffer die (12-Hi)
- Capacity
- 36 GB per stack
- Bandwidth
- 1.2 TB/s per stack
- Price
- $350–400 / stack · ~$10 / GB
What it is
HBM — high-bandwidth memory — is what happens when chip designers decide regular computer memory is too far from the GPU. Twelve dies of DRAM (dynamic random-access memory, the same technology as in a normal laptop) are stacked on top of a buffer die and wired together through microscopic vertical holes called TSVs (through-silicon vias). The whole stack sits millimeters from the GPU, bonded to the same slab of interposer silicon. HBM solves the memory-wall problem that has limited processor performance for twenty years.
Why it matters to an investor
An NVIDIA H100 GPU is only as fast as the memory feeding it — and the memory, not the math, is usually the limit. Every gigabyte of HBM a customer can buy is bandwidth they're renting from Micron, SK hynix, or Samsung. HBM is the single product whose roadmap determines how fast AI models can be served in production. 2026 supply is sold out at rising prices; anyone with incremental capacity earns it.
Reading the tier
Bull case
Micron has been gaining share against SK hynix on HBM3e; HBM4 (2027) roughly doubles bandwidth per stack. Samsung is behind but will qualify eventually, adding more supply.
Bear case
HBM is still an oligopoly of three. Any fab incident or yield problem at one supplier ripples instantly into NVIDIA ship schedules. Micron trades at a notoriously cyclical multiple for a reason.
The signal to watch
Micron, SK hynix, Samsung earnings and HBM-specific disclosures. Industry reports from TrendForce. Anything about "HBM booked through FY28."
Reading the news
Micron quarterly calls. Trendforce and DigiTimes supply checks. When you see "HBM pricing firm into 2H26," memory equities have a tailwind.
Tickers closest to the margin
- MUMicron — most accessible US HBM play
- NVDAconsumes ~50% of the world's HBM
Tier III · Silicon
The module
One GPU, bundled — die, memory, power stage, all on one board.
III
The module
One GPU, bundled — die, memory, power stage, all on one board.
Fig. III — The module. Schematic, not to scale.
- 1Heat spreader — copper IHS
- 2GPU die — 80 B transistors
- 3HBM × 6–8 — on-package memory
- 4Substrate — organic package
- 5SXM5 PCB — mezzanine board
- 6Mezzanine pins — underside · socketed
Specs at a glance
- Form factor
- SXM5 · 78 × 105 mm
- Power draw
- 700–1,000 W
- HBM stacks
- 6 (H100) · 8 (B200)
- Street price
- $25k–40k · RTX 5090: $2–3k
What it is
When an engineer says “an H100,” they usually mean the whole SXM5 module — NVIDIA's proprietary mezzanine form factor. The module is the GPU die bonded to its stacks of HBM (high-bandwidth memory) on a silicon interposer, mounted on a small PCB (printed circuit board) with power delivery, and terminated in a mezzanine connector. The module is the unit everything downstream is designed around. Consumer cards like the RTX 5090 are the same architecture in a smaller, cheaper, slower form factor.
Why it matters to an investor
The module is where NVIDIA captures most of its margin — a $3k die plus $3k of memory, wrapped in $3k of board / power / test, sells for $30k. The SXM form factor is deliberately proprietary; it locks customers into NVIDIA reference designs and into adjacent margin pools (NVLink, NVSwitch, networking).
Reading the tier
Bull case
Blackwell B200 pushes the module to 1,000 W of sustained compute. Modules are the input to every server below — if shipments rise, every partner in the stack benefits.
Bear case
Open-standard OAM (open accelerator module, backed by AMD and Intel) continues to gain enterprise mindshare; Ethernet alternatives to NVLink threaten the moat. Consumer cards get cannibalized during memory shortages.
The signal to watch
Earnings from Supermicro (SMCI) and Dell (DELL) for system shipments; AMD MI300X / MI350 traction; the average-selling-price spread between SXM and OAM modules. Commentary from Taiwan ODMs (original-design manufacturers) like Quanta and Wiwynn is often earliest.
Reading the news
NVDA Data Center segment (quarterly). AMD earnings for Instinct revenue. SuperMicro and Dell for pull-through into servers.
Tickers closest to the margin
- NVDAdesigns and sells the module
- AMDInstinct OAM — open-standard rival
Tier IV · Silicon
The baseboard
Eight GPUs wired together so tightly they act like one giant chip.
IV
The baseboard
Eight GPUs wired together so tightly they act like one giant chip.
Fig. IV — The baseboard. Schematic, not to scale.
- 1SXM5 × 8 — 700–1,000 W ea
- 2NVSwitch × 4 — 900 GB/s fabric
Specs at a glance
- Product
- HGX B200 · 8 × SXM5
- Fabric
- NVLink, 900 GB/s bisection
- Size
- ~544 × 406 mm (21.4 × 16 in)
- Power
- ~6.5 kW (H100) · 10.4 kW (B200)
What it is
The HGX is NVIDIA's 8-GPU reference board. Eight SXM modules share one ultra-fast internal network — NVLink — routed through four NVSwitch ASICs (application-specific integrated circuits). The result is that eight GPUs behave like a single 8-GPU brain for workloads that can use it. Training a frontier model means moving terabytes per second of gradient data between the GPUs; the baseboard is what makes that physically possible inside a single server.
Why it matters to an investor
The baseboard is where a second set of companies earns its keep: signal integrity at 200 Gb/s on NVLink is not trivial, and retimer chips, AOCs (active optical cables), AECs (active electrical cables), and specialized PCBs (printed circuit boards) are their own market. This is the layer where AI infrastructure bleeds out of pure-play GPU economics into an adjacent web of analog and connectivity names.
Reading the tier
Bull case
Every generation of NVLink bandwidth doubles the retimer and AOC market. Astera Labs (ALAB) and Credo (CRDO) have been compounding at >80% revenue growth on this tailwind.
Bear case
NVIDIA could bring retimer functionality in-house (has done so before in adjacent analog domains). AMD and Intel baseboards use slightly different fabrics, diluting the pull-through.
The signal to watch
Quarterly revenue from Astera Labs (ALAB) and Credo (CRDO); commentary about NVLink generation attach rates. The NVL72 rack ramp is a double-order tailwind for both.
Reading the news
ALAB and CRDO earnings. NVLink-C2C vs PCIe Gen6 debates at OCP (Open Compute Project) Summit. Any “attach rate” language on an analog chipmaker's call.
Tickers closest to the margin
- NVDAreference design; NVSwitch ASIC
- ALABAstera Labs — retimers
- CRDOCredo — AECs and AOCs (active electrical & optical cables)
Tier V · Steel
The chassis
Eight GPUs, two CPUs, a rack-mount box that weighs as much as a motorcycle.
V
The chassis
Eight GPUs, two CPUs, a rack-mount box that weighs as much as a motorcycle.
Fig. V — The chassis. Schematic, not to scale.
- 18× GPU status
- 2NVMe bays — 30 TB
- 3Airflow grille
Specs at a glance
- Form factor
- 8U · 482 × 356 × 897 mm
- Weight
- 130.5 kg (287.6 lb)
- Power
- 10.2 kW · 6 × 3,300 W PSUs (power-supply units)
- CPU / RAM
- 2 × Xeon Platinum · 2 TB
What it is
One complete AI server — the unit that actually ships in a crate, gets bolted into a rack, plugged into power, and runs production inference for Meta, Google, or a Fortune-500 bank. DGX is NVIDIA's own brand; HGX is the same thing rebadged by Dell, Supermicro, and HPE. The chassis integrates the baseboard, the CPU tray (which handles I/O and scheduling), eight high-speed NICs (network-interface cards, for talking to other servers), and six redundant PSUs (power-supply units).
Why it matters to an investor
This is the layer where systems integrators earn their margin. A DGX H100 costs NVIDIA maybe $300k to build and sells for $500k. Supermicro has compounded revenue ~90% YoY on AI-server demand; Dell's ISG (Infrastructure Solutions Group) segment rerated accordingly. It is also the first layer where public-company earnings give a clean pulse on actual deployment velocity.
Reading the tier
Bull case
Every hyperscaler capex cycle pulls through SMCI, DELL, and HPE. Taiwan ODMs (original-design manufacturers — Foxconn, Quanta, Wiwynn) benefit equivalently; they ship most of the hyperscaler units directly.
Bear case
Margin is thin at the system level (Supermicro operates at ~15% gross). Supply-chain incidents at ODMs — power-supply shortages, memory hold — ripple immediately. Working capital is demanding.
The signal to watch
SMCI and DELL earnings, commentary on "AI server mix" and "liquid-ready" product share. Foxconn monthly revenue releases.
Reading the news
"Book-to-bill" at SMCI. Dell ISG orders. Any management comment about liquid-ready attach rate.
Tickers closest to the margin
- SMCISupermicro — the specialist builder
- DELLPowerEdge XE9680 line
- HPECray AI servers & ProLiant
Tier VI · Steel
The rack
Seventy-two GPUs plumbed together, in a liquid-cooled box the size of a refrigerator.
VI
The rack
Seventy-two GPUs plumbed together, in a liquid-cooled box the size of a refrigerator.
Fig. VI — The rack. Schematic, not to scale.
- 172 × GPU — 18 trays
- 2NVSwitch — 9 trays
- 3Liquid manifold
Specs at a glance
- Product
- GB200 NVL72
- Population
- 72 Blackwell + 36 Grace
- Fabric
- 130 TB/s NVLink — all 72 act as one
- Power
- 120 kW · 100% liquid-cooled
What it is
NVL72 is NVIDIA's current flagship training unit — a rack that behaves as a single, 72-GPU supercomputer. Eighteen compute trays (each carrying two Grace-Blackwell superchips, so four GPUs) and nine NVLink-switch trays alternate up the rack. There are no fans: every watt of heat leaves through liquid manifolds on the rear, routed to rooftop chillers. A single NVL72 delivers 1.4 exaFLOPS (one quintillion floating-point operations per second) — a level of compute that ten years ago lived only in top-ten supercomputers and now sits on a pallet.
Why it matters to an investor
NVL72 is the reason liquid cooling has gone from niche to mainstream. Vertiv's business grew three-fold on this cycle. Equally important, NVL72 changes the unit of purchase for hyperscalers: they now order racks, not servers, in blocks of thousands. Tier VI is where the AI buildout crosses into pure infrastructure spend.
Reading the tier
Bull case
NVL72 ramp through 2026 pulls through Vertiv (cooling), Arista (scale-out networking), and specialist power names. Next-generation Vera Rubin VR200/VR300 racks keep the cycle going into 2028.
Bear case
Liquid-cooling deployments add construction complexity and lead-time risk — halls that were designed for air-cooled racks need retrofitting. Capex cycles are lumpy; any hyperscaler pause compresses the order book.
The signal to watch
Vertiv orderbook, Arista AI revenue segment, NVIDIA commentary on NVL72 ship count. Utility construction permits in Virginia, Phoenix, and Iowa.
Reading the news
Vertiv quarterly orders. Arista's AI mix. NVDA management color on "rack-scale" deployments.
Tickers closest to the margin
- VRTVertiv — liquid cooling & CDUs (coolant-distribution units)
- ANETArista — scale-out switching
- NVDArack reference design
Tier VII · Steel
The data hall
A warehouse of racks with its own substation and coolant plant.
VII
The data hall
A warehouse of racks with its own substation and coolant plant.
Fig. VII — The data hall. Schematic, not to scale.
- 1Rack rows — hot-aisle pairs
- 2CDU — coolant distribution
Specs at a glance
- Floor area
- 50,000 – 1,000,000 sq ft
- Reference hall
- 60 × 210 m · 135,600 sq ft
- Critical load
- 10 – 100 MW
- Cost per MW
- $10–20M (AI-ready liquid)
What it is
The hall is the unit of buildout. One foundation, one cooling loop, one electrical bus — thousands of racks under a single roof. A frontier training cluster today spans tens of thousands of GPUs across multiple halls on a single campus. This is the tier that turns a chip shortage into a construction project; where architects, electrical engineers, and MEP contractors show up on the earnings calls of AI names.
Why it matters to an investor
Colocation REITs (real-estate investment trusts) — Equinix, Digital Realty — build and lease hall-scale space to hyperscalers, and have rerated sharply on AI demand. Build times and power availability are now the binding constraint: you cannot add GPUs faster than the utility can add transformers.
Reading the tier
Bull case
Multi-year power and lease contracts lock in revenue well into the next decade. Specialist operators (Iron Mountain, Applied Digital) have captured AI-specific mandates at premium rents.
Bear case
AI halls are capital-intensive and power-constrained. Any slowdown in hyperscaler capex pushes absorption out by quarters. Rising rates raise the cost of the long-dated debt that funds construction.
The signal to watch
EQIX and DLR quarterly leasing. Vertiv and Eaton power-equipment backlogs. Utility integrated resource plans (IRPs) in datacenter-heavy states.
Reading the news
REIT leasing commentary (always the AI capacity mix). Power-utility capex forecasts in Virginia, Texas, Ohio.
Tickers closest to the margin
- EQIXEquinix — neutral colo
- DLRDigital Realty — hyperscale
- VRTVertiv — equipment into the hall
Tier VIII · Power
The campus
A small city's worth of electricity, poured into one math problem.
VIII
The campus
A small city's worth of electricity, poured into one math problem.
Fig. VIII — The campus. Schematic, not to scale.
- 1Hall × 5+ — each ≈ 50 MW
- 2Substation — grid tap
- 3HV transmission
Specs at a glance
- Footprint
- hundreds of acres
- Power
- 1 – 10 GW
- Flagship projects
- Stargate, Prometheus, Mount Pleasant
- Capex
- $45–55 B per GW
What it is
A gigawatt campus draws as much electricity as a midsized American city. The bottleneck at this scale is not silicon — it is substations, transmission rights-of-way, and long-dated PPAs (power-purchase agreements) with a specific generator. Stargate, announced in 2025 at $500 billion, targets 10 gigawatts by 2029: the equivalent of ten nuclear reactors dedicated to training the next generation of frontier models.
Why it matters to an investor
This is the end of the AI trade chain. A portfolio thesis that stops at NVIDIA is missing where the marginal capex actually lands: with the generators, the transmission utilities, and the contractors building substations. Nuclear, merchant gas, geothermal, long-distance HVDC (high-voltage direct current) — all of it is now downstream of the same trade.
Reading the tier
Bull case
Nuclear operators with baseload capacity (Constellation's Three Mile Island re-start for Microsoft) have signed 20-year PPAs at a premium. SMRs (small modular reactors, from NuScale and TerraPower) are suddenly fundable. Merchant generators with flexible dispatch (Vistra, Talen) capture peak premiums.
Bear case
Build timelines measured in years, not quarters. Permitting risk is real. Grid operators — PJM (the Pennsylvania-Jersey-Maryland Interconnection) and ERCOT (the Electric Reliability Council of Texas) — have started pushing back on interconnection queue expansions. Any slowdown in hyperscaler capex cascades years-forward into the whole utility stack.
The signal to watch
Hyperscaler announced capex (quarterly). PPA announcements (monthly press). Utility capex plans. FERC (Federal Energy Regulatory Commission) interconnection queue filings. PJM capacity-auction clearing prices.
Reading the news
Every headline about a new hyperscaler campus names a power partner. PJM and ERCOT auction results. Any "nuclear restart" or "SMR grant" press release.
Tickers closest to the margin
- CEGConstellation — nuclear PPAs
- VSTVistra — merchant generation
- TLNTalen Energy — 24/7 baseload
Ticker index — 18 names
The eighteen public equities closest to the margin of the AI buildout, mapped to their primary plate(s). Not a recommended portfolio — a reading list.
| Ticker | Pillar | Plate(s) |
|---|---|---|
| NVDA | Silicon | Tier I, III, IV, VI |
| TSM | Silicon | Tier 0, I |
| ASML | Silicon | Tier 0 |
| AMAT | Silicon | Tier 0 |
| MU | Silicon | Tier II |
| AMD | Silicon | Tier I, III |
| ALAB | Silicon | Tier IV |
| CRDO | Silicon | Tier IV |
| SMCI | Steel | Tier V |
| DELL | Steel | Tier V |
| HPE | Steel | Tier V |
| VRT | Steel | Tier VI, VII |
| ANET | Steel | Tier VI |
| EQIX | Steel | Tier VII |
| DLR | Steel | Tier VII |
| CEG | Power | Tier VIII |
| VST | Power | Tier VIII |
| TLN | Power | Tier VIII |
Glossary of terms
- CoWoS
- Chip-on-Wafer-on-Substrate. TSMC’s advanced packaging that joins a GPU die to HBM stacks via a silicon interposer.
- EUV
- Extreme-ultraviolet lithography. The only way to print features below 7 nm; ASML’s monopoly.
- FinFET / GAA
- Transistor geometries. Vertical-fin (FinFET) used since ~14 nm; gate-all-around (GAA) replaces it starting at 2 nm.
- HBM
- High-Bandwidth Memory. Stacked DRAM dies bonded directly to a compute die. The single most bandwidth-constrained part in the AI stack.
- NVLink
- NVIDIA’s chip-to-chip and chip-to-switch fabric, distinct from PCIe. 900 GB/s of bisection bandwidth on HGX; 130 TB/s on NVL72.
- PPA
- Power Purchase Agreement. A multi-year contract between a data center buyer and a specific power generator.
- PUE
- Power Usage Effectiveness. Ratio of total facility power to IT power. Well-engineered AI halls now run below 1.15.
- SMR
- Small Modular Reactor. Factory-built nuclear units in the 50–300 MW range, well matched to a single AI campus.
- SXM
- NVIDIA’s mezzanine socket standard for datacenter GPUs. Proprietary; the basis of the HGX baseboard ecosystem.
- TSV
- Through-Silicon Via. The copper pillars that pass data vertically through each DRAM die in an HBM stack.
- Hyperscaler
- Amazon, Microsoft, Google, Meta, and a small number of comparable buyers. The vast majority of datacenter GPUs go to them.
- Colo
- Colocation. Wholesale data center space leased from a REIT like Equinix or Digital Realty, typically to a hyperscaler or enterprise.
Colophon & further reading
This document
The AI Infrastructure Atlas, 2026 first edition. Set in Fraunces and Inter Tight with JetBrains Mono for data. Illustrations drawn in pure SVG. Content refreshed annually.
Further reading
• TSMC quarterly earnings & monthly revenue releases
• Micron, SK hynix, Samsung HBM roadmaps
• SemiAnalysis / TrendForce supply-chain notes
• Hyperscaler capex disclosures (MSFT, META, GOOGL, AMZN)
• PJM and ERCOT interconnection queues
• DataCenterFrontier for hall-scale reporting
Keep reading
Company files for all 37 tickers. The interactive Chain. A copy-it-once Watchlist.
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Disclosure
Research only. Not investment advice. Do your own diligence. The author may hold positions in any security mentioned. WattsB4Bots is an educational project and is not registered as an investment advisor.
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