Company File
Custom silicon partner to Google (TPU) and Meta (MTIA); dominant AI networking ASICs.
Plate I — Pillar-Purity Score
Custom silicon + AI networking; hyperscaler-defection hedge.
Methodology — How we score
Plate II — The Thesis
Why it’s on the list.
Broadcom designs the custom silicon behind Google's TPU and Meta's MTIA, plus the dominant AI networking ASICs in hyperscaler switches. The custom-silicon thesis is that hyperscalers defect from Nvidia for inference — and Broadcom captures those dollars.
Plate III — Supply Chain
Upstream & downstream.
See the full chain plate for all 37 names.
Upstream — what feeds AVGO
Downstream — where AVGO feeds into
Plate IV — Thesis Breakers
What would invalidate this.
- Risk 01Hyperscaler in-sources ASIC design
- Risk 02VMware integration drag
Plate V — Also on the Silicon plate
Siblings by pillar.
- NVDAScore 10The king: GPUs, the CUDA moat, Mellanox networking, and the expanding software stack.
- TSMScore 10Fabs every leading-edge AI chip on earth — the real bottleneck of the entire stack.
- ASMLScore 10EUV lithography monopoly; no EUV means no sub-5nm chips.
- ALABScore 10PCIe retimers and CXL connectivity — the glue chips inside every AI rack.
- CRDOScore 10Active electrical cables and SerDes for AI-rack interconnect; pure-play AI networking IC.
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Next earnings: 2026-06-04.
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