Company File
CPU IP inside every hyperscaler's custom silicon — Graviton, Axion, Cobalt.
Plate I — Pillar-Purity Score
CPU IP inside every hyperscaler custom chip.
Methodology — How we score
Plate II — The Thesis
Why it’s on the list.
Arm's ISA is the default CPU IP for every hyperscaler building in-house silicon. Royalty per chip scales with custom-silicon proliferation. SoftBank overhang is a governance, not fundamental, concern.
Plate III — Supply Chain
Upstream & downstream.
See the full chain plate for all 37 names.
Upstream — what feeds ARM
Top of chain within our coverage.
Downstream — where ARM feeds into
Plate IV — Thesis Breakers
What would invalidate this.
- Risk 01RISC-V adoption surges in server
- Risk 02Licensing model disruption
Plate V — Also on the Silicon plate
Siblings by pillar.
- NVDAScore 10The king: GPUs, the CUDA moat, Mellanox networking, and the expanding software stack.
- TSMScore 10Fabs every leading-edge AI chip on earth — the real bottleneck of the entire stack.
- ASMLScore 10EUV lithography monopoly; no EUV means no sub-5nm chips.
- ALABScore 10PCIe retimers and CXL connectivity — the glue chips inside every AI rack.
- CRDOScore 10Active electrical cables and SerDes for AI-rack interconnect; pure-play AI networking IC.
Close
Next earnings: 2026-05-06.
The Sunday brief decodes earnings that matter. Five minutes. Free.
Research only. Not investment advice. Do your own diligence.