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MUMicron Technology
HBM3E memory for Nvidia; memory bandwidth is now the binding constraint on AI performance.
Plate I — Pillar-Purity Score
9/ 10
HBM is the AI binding constraint; Micron a primary supplier.
Methodology — How we score
Plate II — The Thesis
Why it’s on the list.
Memory bandwidth, not compute, is the binding constraint on modern AI workloads. Micron is the only US HBM supplier and the third globally. HBM revenue share is the signal to watch every quarter.
Plate III — Supply Chain
Upstream & downstream.
See the full chain plate for all 37 names.
Upstream — what feeds MU
Downstream — where MU feeds into
Plate IV — Thesis Breakers
What would invalidate this.
- Risk 01HBM4 roadmap slip
- Risk 02SK hynix captures incremental AI share
Plate V — Also on the Silicon plate
Siblings by pillar.
- NVDAScore 10The king: GPUs, the CUDA moat, Mellanox networking, and the expanding software stack.
- TSMScore 10Fabs every leading-edge AI chip on earth — the real bottleneck of the entire stack.
- ASMLScore 10EUV lithography monopoly; no EUV means no sub-5nm chips.
- ALABScore 10PCIe retimers and CXL connectivity — the glue chips inside every AI rack.
- CRDOScore 10Active electrical cables and SerDes for AI-rack interconnect; pure-play AI networking IC.
Close
Next earnings: 2026-06-24.
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Research only. Not investment advice. Do your own diligence.